Modern analog circuit simulators produce a plethora of output reports, often in a variety of file formats. Among these are reports of violations of various types of checks and assertions, such as Property Specification Language (PSL) functional assertions, device Safe Operating Area (SOA) assertions, and various implementation related checks such as static checks and dynamic checks of various kinds (e.g., high impedance node checks, excessive rise/fall time checks, etc. as will be described). For purposes of brevity in this description, all such checks and assertions may be simply referred to as “checks” or “asserts”, and various problematic results indicative of errors and violations may be simply referred to as “violations”. Reports may be written to the primary simulator log file (as one commercial simulator does for its SOA checks), or to “companion” files (e.g., XML files, as one commercial simulator does for its static/dynamic checks).
An analog circuit design environment is responsible for setting up the data and tasks for a given simulator to perform, in addition to allowing the user to efficiently inspect the simulation results, including such output reports, and to debug a circuit design. However, it is a significant burden for the design environment development team to keep up with the various types of files and file formats produced by today's simulators. Modern design environments should ideally be able to easily cross reference items cited in the various output reports back to the schematic database from which the circuit netlist is derived, to facilitate debugging. The differences in simulator output file formats make this task difficult.
Further, each individual type of check supported by the simulator has historically come with its own dedicated graphical user interface (GUI) for inspecting the results of that check. The resulting design environment may often appear non-uniform and disorganized. Basic interaction tasks that users learn for interacting with the check violation data do not usually map across the different types of checks and supported GUIs, therefore increasing the users' cognitive workload. As new checks are added to an often rapidly evolving simulator, the design environment can often “fall behind” due to being on different release schedules. The result may be that no design environment user interface may exist at all for newer checks until quite some time after the simulator has been released. Without such user interfaces, users usually have to resort to manually viewing simulator log files and other inefficient methods of managing simulator output.
Thus, there is a need for an improved approach to viewing and understanding analog simulation check and assertion violations and related errors in a design environment. Accordingly, the inventors have developed a novel way to help circuit designers and design tool vendors address this issue.